Methods and apparatus for efficient linear combiner

ABSTRACT

In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This continuation application claims priority to U.S. patent applicationSer. No. 15/645,647, filed Jul. 10, 2017, which application claimspriority to and the benefit of India Provisional Patent Application No.201641024045, filed Jul. 14, 2016, both of which are hereby incorporatedherein by reference.

TECHNICAL FIELD

This application relates generally to linear combination of signals.

BACKGROUND

Linear combiners, such as digital filters, have many uses in signalprocessing. One of those uses is with RF sampling receivers. RF samplingreceivers convert an analog RF signal directly to a digital signal,thereby eliminating RF local oscillators (LO), mixers, gain stages andfilters. A wide range of applications use this type of receiverincluding 3G/4G base station receivers, software-defined radio (SDR) andhigh performance test equipment.

RF sampling typically uses an interleaved analog-to-digital converter(ADC). For example, a device may use 4 ADCs sampling alternately at 750million samples per second (MSPS) to realize a 3 billion (giga-) samplesper second (GSPS) ADC. That is, while one ADC is latching an input, theother three ADCs are processing their inputs. Thus, the four ADCsprocess four inputs for each period and the combined throughput is 4×750MSPS or 3 GSPS.

However, it is difficult to perfectly match ADCs. A typical mismatch isa difference in gain and phase at different frequencies. An interleaving(IL) mismatch corrector can correct spurs caused by IL mismatches.Examples of mismatch correctors can be found in co-owned U.S. Pat. Nos.7,916,051 and 7,915,050, which are hereby fully incorporated herein byreference. The mismatches are typically frequency dependent and need alinear corrector or filter of many coefficients or “taps.” For example,a 3 GSPS ADC using a 750 MSPS ADCs typically will use a filter of 32taps for each component ADC.

However, many applications for linear combiners, such as digitalfilters, must have very low power consumption. The large number of tapsand the complex mathematical functions implemented by the combiners makethis difficult to achieve.

SUMMARY

In accordance with an example, an integrated circuit includes a linearcombiner having an input for receiving a signal. The linear combineralso has a plurality of operator circuits for applying weighting factorsto the signal, in which a first operator in the plurality of operatorcircuits performs a first operation on the signal using a firstsub-weight of one of the weighting factors to provide a first tileoutput and a second operator circuit in the plurality of operatorcircuits performs a second operation on the signal using a secondsub-weight of the one of the weighting factors to provide a second tileoutput. The linear combiner also has an adder having a first inputcoupled to receive the first tile output and the second tile outputs andproviding a combined output.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a high throughput analog to digitalconverter (ADC).

FIG. 2 is a schematic diagram of a linear correction circuit thatcorrects for mismatches in the response of interleaved ADCs.

FIG. 3 is a schematic diagram of a finite impulse response (FIR) filter.

FIG. 4 is a graph showing four example sets of weighting factors.

FIG. 5 is a graph of an example weighting factor configuration.

FIG. 6 is a block diagram of an example linear combiner.

FIG. 7 is a schematic diagram showing a data flow through a linearcombiner.

FIG. 8 is a block diagram of an example ADC interleaving corrector.

FIG. 9 is a flowchart of an example method.

FIG. 10 is an example method for performing a step of the method of FIG.9.

DETAILED DESCRIPTION

Corresponding numerals and symbols in the different figures generallyrefer to corresponding parts unless otherwise indicated. The figures arenot necessarily drawn to scale.

The term “coupled” may include connections made with interveningelements, and additional elements and various connections may existbetween any elements that are “coupled.” The term “plurality” as usedherein means two or more.

FIG. 1 is a block diagram of a high throughput analog to digitalconverter (ADC) 100. Differential inputs 101 feed buffers 102 and 104.Each of ADCs 106, 108, 110 and 112 has a throughput of 750 millionsamples per second (MSPS). Therefore, the combined throughput is 3giga-samples per second (GSPS). ADCs 106, 108, 110 and 112 operate underthe control of clock divider 116. Differential clock inputs CLKP 118 andCLKM 120 drive clock divider 116. To provide 3 GSPS throughput, ADCs106, 108, 110 and 112 sample the input signal serially, one at a time.Buffers 102 and 104 insure that each of ADCs 106, 108, 110 and 112 hasthe appropriate input when necessary. That is, buffers 102 and 104 alongwith clock divider 116 cause ADCs 106, 108, 110 and 112 to provide aninterleaved output signal with a combined sampling rate of 3 GSPS.Digital estimation and correction block 114 combines the outputs of ADCs106, 108, 110 and 112 as a single output. The use of four ADCs is anexample. The number of interleaved ADCs is only limited by practicalconsiderations of implementation.

However, it is very difficult to make four ADCs with the same responsecharacteristics. One ADC may have a gain of x at a frequency and thenext ADC may have a gain of x*1.02 at that frequency. Even smallmismatches create frequency spurs in the overall ADC output that cancause significant performance problems in downstream processing of thatoutput.

FIG. 2 is a schematic diagram of an interleaving mismatch correctioncircuit 200 that corrects for mismatches in the response of interleavedADCs, such as ADCs 106, 108, 110 and 112 (FIG. 1). Circuit 200 can beimplemented in hardware or software. In an example, digital estimationand correction block 114 (FIG. 1) is an integrated circuit that includescircuit 200 implemented in hardware. ADC output x(n) 201 is thecombined, interleaved output of ADCs 106, 108, 110 and 112 (FIG. 1).Delay unit 202 and linear combiners 204, 206 and 208 receive ADC outputx(n) 201. One ADC, for example ADC 106 (FIG. 1), is a reference ADC. Theoutput of this ADC passes through circuit 200 uncorrected. Delay unit202 is a tapped delay line that delays this output to align it in timewith the output of the other ADCs because of the delays caused by linearcombiners 204, 206 and 208.

Linear combiners 204, 206 and 208, in this example, are multi-tap finiteimpulse response (FIR) filters. For example, linear combiner 204 mayprovide correction for ADC 108 (FIG. 1), linear combiner 206 may providecorrection for ADC 110 (FIG. 1), and linear combiner 208 may providecorrection for ADC 112 (FIG. 1).

Switches 216, 218 and 220 coordinate so that the output of linearcombiners 204, 206 and 208 arrive at subtraction unit 222 at the sametime as the ADC output for the corresponding ADC. The output of linearcombiners 204, 206 and 208 is a correction factor for the output of ADCs108, 110 and 112 (FIG. 1), respectively. The respective correctionfactor arrives at subtraction unit 222 at the same time as the output ofthe respective ADC and corrects for the mismatch between that ADC andthe reference ADC.

FIG. 3 is a schematic diagram of a finite impulse response (FIR) filter300. An FIR filter is one example of a linear combiner. As notedhereinabove, linear combiners 204, 206 and 208 (FIG. 2) may be FIRfilters. Input 301 corresponds to the input to one of linear combiners204, 206 and 208 (FIG. 2). Operator circuits, such as delay unit 302-0and multiplier 304-0 receive input 301. Delay unit 302-1 and multiplier304-1 receive the output of delay unit 302-0. This pattern repeats untilonly multiplier 304-n-1 receives the output of delay unit 302-n-2. Theinteger n is the number of weighting factors or taps in the filter.Multipliers 304-0 through 304-n-1 multiply the respective inputs withtaps 305-0 through 305-n-1, respectively. A tap is a number selected toprovide the desired filter response according to FIR filter theory.Adders 306-1 through 306-n-1 add the outputs of multipliers 304-0through 304-n-1 to provide correction output 308.

FIG. 4 is a graph showing the bit size (i.e., the bit width needed todesign a filter) for four example sets of weighting factors or taps liketaps 305-0 through 305-n-1 (h₀ through h_(n-1)) (FIG. 3). In thisexample, the weighting factors are filter taps. Filter 402 is for a highADC mismatch with no delay correction. Filter 404 is for a high ADCmismatch with delay correction. Filter 406 is for a medium ADC mismatchwith no delay correction. Filter 408 is for a medium ADC mismatch withdelay correction. Graph 400 shows that each of the filter tap setsincludes, in this example, 32 filter taps. The vertical axis of graph400 indicates the number of bits needed to represent the filter tap.Graph 400 shows that the number of bits needed for various taps has agreat variation from less than two to twelve. Each one of the tapsillustrated in graph 400 corresponds to a multiplier in FIR 300 (FIG.3). Each correction circuit 200 (FIG. 2) includes three filters, such aslinear combiners 204, 206 and 208 (FIG. 2). Therefore, the describedexamples include 3*32=96 multipliers. A worst case bit width of 12-bitsper tap may be used to implement the filters. In such a case, eachmultiplier multiplies a 12-bit tap with a 9-bit ADC input, and thus is a12×9 multiplier. Each of these multipliers performs a multiplicationevery 1/750 MHz=1.34 nS. This consumes a very large amount power.

FIG. 5 is a graph 500 of an example weight factor or tap configuration.The taps shown in graph 500 are similar to the taps shown in graph 400.Each tap or weight is divided into sub-weights according to the numberof bits in the tiles. High tile 502 includes the most significant bits9-11 of the taps. Medium tile 504 includes bits 4-8 of the taps. Lowtile 506 includes bits 0-3 of the taps. The tiles are not simply therespective bits. Binary numbers are usually represented in complexconfigurations such as 2's complement to allow for simpler and/or fastercircuitry to perform mathematical functions. With such complex binarynumber configurations, simply removing the medium and low bits from tapsmay separate those bits from the sign bit(s) and change the numericvalue of those groups of bits.

Therefore, the sub-weights in tiles 502, 504 and 506 must be determinedin a manner that preserves the overall value of the weight (tap). In oneexample, the medium and low tile sub-weights may be the correspondingbits with an added sign bit to preserve their value. In another example,a rounding procedure accounts for the sign while preserving the overallvalue of the weight without the need to add additional sign bits. Toexplain this example, assume that the weight h is the binary number010100011001, which is expressed in 2's complement format. Convertingthe weight to sub-weights in this example uses the following scaled,rounding-based decomposition procedure.

First, the eight most significant bits of the weight h are removed toproduce the low tile weight h_(L). This is expressed mathematically inEquation 1:

h _(L) =h&0xF  (1)

Where, & represents the Boolean AND function and 0xF is the hexadecimalrepresentation of the binary number 000000001111. That is, 0xF has zerosin the bit positions to be removed and ones in the bit positions to bepreserved.

Second, the weight h is truncated to a weight h_(HM) including the highand medium bits and where the least significant bit of h_(HM) isrounded. That is, if the most significant bit of h_(L) is one, a one isadded in the least significant bit position of h_(HM). Using the aboveexample weight, h is 010100011001, the bottom four bits are removed,which truncates to 01010001. Because the most significant bit of h_(L)is 1, rounding adds a one in the least significant bit position to yield01010010. This is expressed mathematically in Equation 2:

h _(HM)=round(h,4)  (2)

In this case, the number of bits rounded is four.

In this example, h_(L) is 1001. In 2's complement notation, that is −7.However, these bits represent 9 in weight h. To correct for this, a onein the least significant bit position of h_(HM) (2⁴) is added byrounding. That is, 16 is added to h_(HM). The added 16 compensates forthe change in value of the h_(L) because of the 2's complement format.That is, 16 added to negative 7 equals the original value of 9. Thus,the rounding operation preserves the original value without the need toadd an additional sign bit to h_(L). If the leading bit of h_(L) iszero, the original value of the low tile bits and the 2's complementrepresentation are the same. Therefore, whether the most significant bitof h_(L) is 0 or 1, the four bits of h_(L) can be used as a 2'scomplement number without the need to add a sign bit or any otheralteration.

Third, the medium tile sub-weight h_(M) is determined by removing thethree most significant bits of h_(HM). This is expressed mathematicallyin Equation 3:

h _(M) =h _(HM)&0x1F  (3)

Where 0x1F is the hexadecimal representation of 31 or 00011111

Fourth, the high tile sub-weight h_(H) is determined by rounding h_(HM)to the high tile bits. In this example, the lower five bits of h_(HM)are rounded off. This is expressed mathematically in Equation 4:

h _(H)=rounded(h _(HM),5)  (4)

In the above example, h_(HM) is 01010010, which is truncated to 010. Themost significant bit of h_(M) is one, so a one is added in the leastsignificant bit position of h_(H) to yield h_(H)=011. As with the lowtile sub-weight, the rounding of h_(H) allows h_(M) to be used as a 2'scomplement number without alteration (that is, no added sign bit isnecessary).

These numbers added together provide the correct weight or tap. Thisprovides the correct result because of the distributive property oflinear functions. In this case, this can be expressed as Equation 5 and6:

h=(h _(H)*2^((b) ^(M) ^(+b) ^(L) ⁾ +h _(M)*2^((b) ^(L) ⁾ +h _(L))  (5)

Where b_(M) is the number of bits in h_(M) and b_(L) is the number ofbits in h_(L). Therefore,

hx(n)=h _(H)*2^((b) ^(M) ^(+b) ^(L) ⁾ +h _(M)*2^((b) ^(L) ⁾ +h_(L))x(n)=(h _(H)*2^((b) ^(M) ^(+b) ^(L) ⁾)x(n)+(h _(M)*2^((b) ^(L)⁾)x(n)+h _(L) x(n)  (6)

Where x(n) is the input digital signal from the ADCs.

FIG. 6 is a block diagram of an example linear combiner 600. Linearcombiner 600 may have all or a portion of its components in anintegrated circuit or multiple integrated circuits in a hybrid package.In addition, a processor such as a digital signal processor mayimplement all or a portion of the components of linear combiner 600.Linear combiner 600 performs a function like one of linear combiners204, 206 or 208 (FIG. 2). Dithered quantizer 602 receives ADC outputx(n) 601. As noted hereinabove regarding FIG. 2, ADC output x(n) 601 maybe, for example, 15 bits. Dithered quantizer 602 quantizes ADC outputx(n) 601 to a lower precision by truncating it to a lower number bits,for example, truncating the lower 6 bits of ADC output x(n) 601.Therefore, the output of dithered quantizer 602 is the 9 mostsignificant bits of ADC output x(n) 601. Mathematics, simulations and/orexperimentation determine the allowable level of truncation that avoidsthe addition of significant noise to the final output.

High tile combiner 610 is, in this example, a finite impulse response(FIR) filter like FIR 300 (FIG. 3). However, the taps that are appliedto high tile combiner 610 are the sub-weights of high tiles 502 (FIG.5). Therefore, each multiplication in high tile combiner 610 is anine-bit input times a three-bit high tile filter quantity. Themultipliers 304-1 through 304-1 (FIG. 3) are 9-bit (input)×12(coefficient) multipliers whose complexity is proportional to 9×12=108.Finally, up-shifter 611 shifts the output of high tile combiner 610higher the number of bits in the corresponding the bit size of mediumtile 504 (FIG. 5) and low tile 506 (FIG. 5) to provide a high tilecorrection output. In this example, the taps of high tile 502 (FIG. 5)implicitly include eight zero bits. Therefore, up-shifter 611 shifts theoutput of high tile combiner 610 eight bits.

Graph 500 (FIG. 5) shows that most of high tiles 502 (FIG. 5) are zero.That is, the tap from which high tiles 502 (FIG. 5) is derived has avalue lower than 2⁸, in this example. In some examples, when themultipliers of high tile combiner 610 (like the multipliers in the FIRfilter of high tile combiner 610 that correspond to multipliers 304-0through 304-n-1 FIG. 3) have a tile input of zero, high tile combiner610 provides a multiplier output of zero and blocks the clock signalsdriving that multiplier so that multiplier does not operate. Evenmultiplying by zero can consume considerable energy. By blocking theclock of the multipliers that are multiplying zero saves significantpower with no impact on the quality of the filter output.

Dithered quantizer 604 quantizes ADC output x(n) 601 to a lowerprecision by truncating the lower bits of ADC output x(n) 601 by, forexample, 9 bits, three bits more than dithered quantizer 602. The tapsin medium tile 504 (FIG. 5) represent the values of bits 5-8 of the fulltap and feed medium tile combiner 612. The larger truncation by ditheredquantizer 604 does not cause intolerable levels of noise as opposed tothe smaller truncation of dithered quantizer 602, because up-shifter 613shifts the output of medium tile combiner 612 by five fewer bits.Therefore, the output of up-shifter 613 is a smaller number and lesssignificant in the final outcome. Medium tile combiner 612 includes anFIR filter like FIR filter 300 (FIG. 3). As with high tile combiner 610,the combination of the tiled sub-weights and the truncated input ofdithered quantizer 604 allows for smaller 5×6 multipliers in the FIR ofmedium tile combiner 612. The output of up-shifter 613 is a medium tilecorrection output that is added to the output of up-shifter 611 by adder618. As with high tile combiner 610, for any tile that is zero, mediumtile combiner 612 may, in some examples, provide a zero multiplieroutput and block the operation of that multiplier.

Multiplier 608 scales and multiplies ADC output x(n) 601 by a factor α.Dithered quantizer 606 receives the output of multiplier 608 andprovides the top three bits of the a adjusted ADC output x(n) 601 to lowtile combiner 614. The a factor is a number less than one, for example,0.75. Dithered quantizer 606 quantizes ADC output x(n) 601 to a lowerprecision by truncating the lower bits of ADC output x(n) 601 by, forexample, 12 bits, three bits more than dithered quantizer 604. Themultiplication by a is done to ensure that the heavy truncation of theinput does not cause saturation. For example, if the input is 0.9 of thefull scale of the input, quantizing such an input to only the 3 mostsignificant bits results in saturation of the input. Due to thissaturation, a spur arises at the output. To avoid such a spur, the inputis scaled. In this example, multiplying 0.9 by 0.75 makes the inputsmall enough so as to not be saturated. The sub-weights in low tile 506(FIG. 5) represent the values of bits 1-4 of the full tap and feed lowtile combiner 614. As with the medium tile branch, the larger truncationby dithered quantizer 606 does not cause intolerable levels of noise asopposed to the smaller truncation of dithered quantizers 602 and 604,because the output of low tile combiner 614 is not up-shifted.Therefore, the output of low tile combiner 614 is a smaller number andless significant in the final sum. Low tile combiner 614 includes an FIRfilter like FIR filter 300 (FIG. 3). As with high tile combiner 610 andmedium tile combiner 612, the combination of the tiled taps and thetruncated input of dithered quantizer 604 allows for smaller 4×4multipliers in the FIR of low tile combiner 614. Multiplier 616 operatesas a descaler and multiplies the output of low tile combiner 614 withthe inverse of a to compensate for the initial multiplication by a andprovide a low tile correction output.

Adder 620 adds the output of multiplier 616 to the output of adder 618to provide a combined correction output. The combined correction factorcombines with the delayed ADC output x(n) 601 in a similar manner to oneof combiners 204, 206 or 208 to correct delayed ADC output x(n) 601. Thecombiners of FIG. 6 have 9×3 multipliers for the high tile (high tilecombiner 610), 6×5 multipliers for medium tile (medium tile combiner612) and 3×4 multipliers for low tile (low tile combiner 614). Thus, theoverall complexity is 9×3+6×5+3×4=27+30+12=69, which is about 35% lowerin complexity than the original corrector (69 compared with 108).

FIG. 7 is a schematic diagram 700 showing a data flow through a linearcombiner like linear combiner 600 (FIG. 6). For a high tile flow,dithered quantizer 602 (FIG. 6) quantizes ADC output x(n) 701 to a lowerprecision of nine bits, for example by truncating the lower bits of ADCoutput x(n) 701 to truncated output 704. Multiplier 708 multipliestruncated output 704 by high tile sub-weight 706. For the medium tileflow, dithered quantizer 604 (FIG. 6) quantizes ADC output x(n) 701 to alower precision of six bits, for example, by truncating the lower bitsof ADC output x(n) 701 to provide truncated output 710. Multiplier 714multiplies truncated output 710 by medium tile sub-weight 712. For thelow tile flow, multiplier 716 multiplies ADC output x(n) 701 by a.Dithered quantizer 606 (FIG. 6) quantizes ADC output x(n) 701 to a lowerprecision of three bits, for example, by truncating the output ofmultiplier 716 to three bits to truncated output 718. Multiplier 722multiplies truncated output 718 by low tile sub-weight 720. In someexamples, high tile sub-weight 706 may be 3 bits, medium tile sub-weight712 may be 5 bits, and low tile sub-weight 720 may be 4 bits.

Shifter 726 shifts the output of multiplier 708 to compensate the bitpositions below high tile sub-weight 706 that are part of the full tap734. Shifter 728 shifts the output of multiplier 714 to compensate forbit positions below medium tile sub-weight 712 that are part of the fulltap 734. Adder 730 adds the outputs of shifters 726 and 728. Multiplier724 multiplies the output of multiplier 722 by the inverse of a, andadder 732 adds the output of multiplier 724 to the output of adder 730.The output of adder 732 is the correction factor applied to the ADCoutput stream as further explained below.

FIG. 7 is a simplification for clarity. In an actual example using anFIR filter, linear combiner 600 (FIG. 6) applies, as in the example ofgraph 500 (FIG. 5), thirty-two taps 734 to thirty-two multipliers foreach of multipliers 708, 714 and 722 in the configuration of, forexample, multipliers 304-0 through 304-n-1, where n=32. That is, each ofmultipliers 708, 714 and 722 represent thirty-two multipliers (or asmaller number of multipliers used repeatedly to provide thirty-twomultiplications). Each of the high tile combiner 610, medium tilecombiner 612 and low tile combiner 614 (FIG. 6) applies the tiles oftaps like taps 305-0 through 305-n-1 (h₀ through h_(n-1)). FIG. 7 doesnot show delay units 302-0 through 302-n-2 and adders 306-1 through306-n-1 (FIG. 3). However, in the example configuration, each of thehigh tile combiner 610, medium tile combiner 612 and low tile combiner614 (FIG. 6) includes the elements as shown in FIG. 3.

FIG. 8 is a block diagram of an example ADC interleaving corrector 800.ADC interleaving corrector 800 may have all or a portion of itscomponents in an integrated circuit or multiple integrated circuits in ahybrid package. In addition, a processor, such as a digital signalprocessor may implement all or a portion of the components of ADCinterleaving corrector 800. ADC output x(n) 801 includes the output offour interleaved ADCs like ADCs 106, 108, 110 and 112 (FIG. 1). As notedherein above, the output of one of the ADCs is a reference output. Afterthe delay of delay unit 802, this output arrives at subtractor 822 attime 4 p, where p is a sample index from the ADCs (ADCs 106, 108, 110and 112 of FIG. 1). At 4 p+1, the output of the next ADC (for example,ADC 108 (FIG. 1)) arrives at subtractor 822. At 4 p+1, switch 816closes. Thus, linear combiner 804 applies a correction factor tosubtractor 822 to adjust the output of ADC 108 (FIG. 1). At 4 p+2, theoutput of the next ADC (for example, ADC 110 (FIG. 1)) arrives atsubtractor 822. At 4 p+2, switch 818 closes. Thus, linear combiner 806applies a correction factor to subtractor 822 to adjust the output ofADC 110 (FIG. 1). At 4 p+3, the output of the next ADC (for example, ADC112 (FIG. 1)) arrives at subtractor 822. At 4 p+3, switch 820 closes.Thus, linear combiner 808 applies a correction factor to subtractor 822to adjust the output of ADC 112 (FIG. 1). The cycle then repeats.

Linear combiners 804, 806 and 808 include, in this example, three-tilecombiners like linear combiner 600 (FIG. 6). Interleave (IL) mismatchestimator 832 estimates the mismatches between ADCs based onexperimental data, on-chip estimation, simulations, and the frequency,amplitude and other characteristics of ADC output x(n) 801. Correctionfilter generator 834 generates filter characteristics (number of taps,tap amplitude, etc.) and provides this data to dynamic tile optimizer830. Dynamic tile optimizer 830 generates sub-weights 824 (likesub-weights of high tiles 502, medium tiles 504 and low tiles 506 (FIG.5)), filter length 826 and clock/data gating 828 from the output ofcorrection filter generator and provides that data to linear combiners804, 806 and 808.

FIG. 9 is a flowchart of an example method 900. Step 902 provides filtervalues including at least two weights or taps. For example, FIG. 4 showsfour filters 402, 404, 406 and 408, where each filter includesthirty-two taps. Step 904 divides the taps into at least sub-weightscorresponding to two tiles. For example, FIG. 5 shows the weights ofFIG. 4 divided into three tiles 502, 504 and 506. Step 906 applies thesub-weights using a linear combiner for each tile to determine acorrection factor output for a signal. For example, linear combiner 600includes high tile combiner 610, medium tile combiner 612 and low tilecombiner 614 (FIG. 6) to apply the sub-weights of high tile 502, mediumtile 504 and low tile 506 (FIG. 5), respectively, to determine acorrection factor output for each tile. Step 908 combines the correctionfactor outputs determined in step 906 to provide a combined correctionfactor output. For example, adders 618 and 620 combine the outputs ofhigh tile combiner 610 as shifted by up-shifter 611, medium tilecombiner 612 as shifted by up-shifter 613, and low tile combiner asdescaled by multiplier 616. Step 910 corrects the signal using thecombined correction factor output by adding or subtracting thecorrection factor as described regarding subtractor 822 (FIG. 8).

FIG. 10 is an example method 1000 for performing step 906 of method 900(FIG. 9). Step 1002 determines if the sub-weight of the current tap inthe currently operating tile is zero. If not, step 1004 uses thesub-weight to determine a partial product. For example, the output ofone of multipliers 304-0 through 304-n-1 (FIG. 3) is a partial product.If the sub-weight for the current tap is zero, step 1006 sets thepartial product to zero and disables the linear function (for example,one of multipliers 304-0 through 304-n-1 FIG. 3) to save power. Forexample, if one of the sub-weights in high tiles 502 (FIG. 5) is zero,the corresponding one of multipliers 304-0 through 304-n-1 (FIG. 3) isdisabled to save power. If all of the sub-weights in a tile are zero,then all of the multipliers for that tile are disabled. Step 1008combines the partial product determined in either step 1004 or step 1006with previous partial products. Step 1010 determines if the current tapis the last tap. If not, the method loops back to step 1002. If it isthe last tap, step 1012 outputs the combined partial products as thelinear correction factor for the tile.

Modifications are possible in the described examples, and other examplesare possible, within the scope of the claims. For example, althoughexamples described herein employ finite impulse response filters, otherexamples may use other types of filters or other types of linearcombiners.

What is claimed is:
 1. An interleaved analog-to-digital converter (ADC)comprising: a plurality of buffers; a plurality of analog-to-digitalconverters (ADC) coupled to the plurality of ADCs; a linear combinercoupled to the plurality of ADCs; and a clock divider, the clock dividercoupled to a clock signal and the plurality of ADCs; wherein the clockdivider causes the plurality of ADCs to provide an interleaved outputsignal to the linear combiner.
 2. The interleaved ADC of claim 1 whereinthe linear combiner comprises: an input operable to receiving theinterleaved output signal; a plurality of operator circuits operable toapply weighting factors to the interleaved output signal, in which afirst operator circuit in the plurality of operator circuits performs afirst operation on the interleaved output signal using a firstsub-weight of one of the weighting factors to provide a first tileoutput and a second operator circuit in the plurality of operatorcircuits performs a second operation on the interleaved output signalusing a second sub-weight of the one of the weighting factors to providea second tile output; an adder having a first input coupled to receivethe first tile output and the second tile output and providing acombined output; and a scaler coupled between the input and the secondoperator circuit and a descaler coupled to an output of the secondoperator circuit.
 3. The interleaved ADC of claim 2 in which the firstsub-weight and second sub-weight are computed from bits of the one ofthe weighting factors.
 4. The interleaved ADC of claim 2 in which theoperator circuits are multipliers.
 5. The interleaved ADC of claim 2 inwhich the first tile output is shifted upwards by a number of bitscorresponding to bits in the second sub-weight.
 6. The interleaved ADCof claim 2 in which the linear combiner is a filter.
 7. The interleavedADC of claim 2 in which the first operator circuit is disabled when thefirst sub-weight is zero.
 8. The interleaved ADC of claim 21 in whichthe one of the weighting factors is in 2's complement format and thesecond sub-weight is a first number of least significant bits and thefirst sub-weight is a second number of bits beginning with a next mostsignificant bit after the first number of least significant bits that isrounded depending on a value of a most significant bit of the firstnumber of least significant bits.
 9. The interleaved ADC of claim 2 inwhich the plurality of operator circuits includes a third operatorcircuit in the plurality of operator circuits that performs a thirdoperation on the signal using a third sub-weight of the one of theweighting factors.
 10. The interleaved ADC of claim 2 in which thesignal is quantized to a lower precision for the first operation on thesignal.